Alongside sparse RDNA 4 graphics card details and somewhat denser mobile chip yono arcade announcements, AMD also announced the 9 9950X3D and 9900X3D this . Much like their 7000-series counterparts, however, and despite each CPU having two Core Complex Dies (CCDs) full of CPU cores, only one of the two CCDs has 3D V-Cache stacked underneath or on top (underneath for 9000X3D chips and on top for 7000X3D ones).

This, however, doesn't seem to be due to any technical limitations, but just because it's not worth it. HardwareLuxx says it and "the answer was surprising: there are no technical reasons or challenges" why "we haven't seen a Ryzen processor with two CCDs and 3D V-Cache on each of the CCDs."

Apparently, "such a processor would simply be too expensive and games would not benefit from a second CCD with 3D V-Cache to the same extent as the step from 32 to 96 MB L3 cache for one CCD."

The AMD , the current , has just one CCD and 64 MB of 3D V-Cache that sits underneath it. This 3D-stacked cache is great for gaming, which is very cache-consumptive.

The just-announced Ryzen 9 9900X3D and 9950X3D, however, have two CCDs—the former with six cores per CCD and the latter with 8 cores per CCD. But the 3D V-Cache sits underneath just one of these chiplets, which means the top-end 9950X3D has the same 64 MB of 3D V-Cache as the , and only 8 of its cores (again, like the 9800X3D) access it.

The benefit of this is twofold. First, the cores on the CCD without the chiplet can boost to a higher clock speed. Second, there are more cores, which is great for applications that require lots of multicore performance. Crucially, with the 9950X3D at least, in addition to these two benefits, we should also get similar gaming performance to the 9800X3D, given it still has eight cores with access to 64 MB of 3D V-Cache.

That's the theory, anyway. In practice, performance will depend on how well software handles picking between cores with access to 3D V-Cache and faster cores that lack such access. CPU core scheduling can cause issues, which was noted with the 7900X3D and 7950X3D.

One might naturally think the next step would be to chuck stacked cache underneath both chiplets. However, as AMD points out to HardwareLuxx, there's little benefit to doing so as it's "too expensive and games would not benefit."

That's primarily because thread schedulers try to keep all game threads running on the cores of a single CCD regardless. And inter-CCD latency is so high that it would make no sense for these cores to reach across to the other chiplet's stacked cache. As AMD reportedly says, games wouldn't benefit.

Which isn't to say that nothing would benefit. As HardwareLuxx points out, "there are applications that would definitely benefit from yono business 192 MB of L3 cache with 16 cores." But a game won't be one of them, and AMD has clearly—until now, at least—judged that the market for those applications that might benefit isn't big enough to economically justify making dual-stacked X3D chips.